1. Field of the Invention
The present invention relates to a semiconductor device having a protection circuit for preventing an internal circuit from destroying due to an excess voltage, and, more particularly, to a semiconductor device having a protection circuit capable of improving a protective withstand voltage.
2. Description of the Related Art
An input end and output end of an internal circuit in a semiconductor device are respectively provided with an input protection circuit and an output protection circuit for preventing said internal circuit from destroying due to an excess voltage. Recently, a semiconductor device which is designed for higher integration and higher density by reducing the occupying area of a protection circuit has been proposed by Thomas L. Polgreen et al. in "Improving the ESD Failure Threshold of Silicided n-MOS Output Transistors by Ensuring Uniform Current Flow," IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 39, No. 2, February 1992, pp. 382-384.
FIG. 1A is a circuit diagram showing a conventional input protection circuit. FIG. 1B is a circuit diagram showing a conventional output protection circuit. As shown in FIG. 1A, the input protection circuit located on the input end of an internal circuit has a P-channel MOS transistor 42 and an N-channel MOS transistor 43 connected in series. A line 61 is connected between the transistor 42 and the transistor 43. One end of the line 61 is connected to a pad electrode 41 and the other end of the line 61 is connected via an inverter 44 to a buffer output end 45.
As shown in FIG. 1B, the output protection circuit located on the output end of the internal circuit has a P-channel MOS transistor 47 and an N-channel MOS transistor 48 connected in series. A line 62 is connected between the transistors 47 and 48 to which a pad electrode 46 is connected via the line 62.
FIG. 2A is an exemplary diagram showing the N-channel MOS transistor 43 in the input protection circuit shown in FIG. 1A. FIG. 2B is an exemplary diagram showing the N-channel MOS transistor 48 in the output protection circuit shown in FIG. 1B. FIG. 3 is an exemplary diagram depicting a cross section along the line IIA--IIA in FIG. 2A. As shown in FIGS. 2A and 3, a plurality of gate electrodes 51 extending in parallel are formed on the semiconductor substrate 56. Drain diffusion layers 52 and source diffusion layers 53 are alternately formed at the surface of the semiconductor substrate 56 between those gate electrodes 51 and on both sides of the gate electrodes 51.
Drain electrodes 52a and source electrodes 53a, extending in parallel to the gate electrodes 51, are formed via insulator films (not shown) on the drain diffusion layers 52 and the source diffusion layers 53. Those electrodes 52a and 53a are electrically connected to the associated drain diffusion layers 52 and source diffusion layers 53 via contacts 54, which are selectively formed at the insulator films. Further, the drain electrodes 52a are connected in parallel to the line 61, and the pad electrode 41 is connected to one end of the line 61 with the buffer output end 45 connected to the other end of the line 61. Furthermore, the source electrodes 53a and the gate electrodes 51 are set to a ground (GND) potential 55.
A P type guard ring layer 58 which is set to the GND potential is formed at the surface of the semiconductor substrate 56 at such a position as to surround those MOS transistors, with field oxide films 57 formed at both sides of this guard ring layer 58.
As shown in FIG. 2B, the N-channel MOS transistor 48 in the output protection circuit has the same structure as the N-channel MOS transistor 43 of the input protection circuit.
In the conventional protection circuits, the gate width of an MOS transistor which is used as a buffer transistor is normally about 400 .mu.m, significantly larger than the gate width of MOS transistors of the internal circuit. The large gate width is for discharging a large current of about 1 A, applied to the pad, to the GND potential.
In the prior art illustrated in FIGS. 2A, 2B and 3, the protection circuit is not comprised of a single transistor, but has a plurality of transistors connected in parallel so that the substantial gate width of the whole transistors becomes about 400 .mu.m. The thus designed protection circuit can make its occupying area smaller than that of the protection circuit, which has a single MOS transistor with the same gate width. This can accomplish high integration and high density of a semiconductor device.
FIG. 4 is a graph showing the snapback characteristic of a buffer transistor with the input current plotted on the vertical scale and the input voltage plotted on the horizontal scale. It is to be noted that a solid line 71 in the figure shows the snapback characteristic of a silicided device while a broken line 72 in the figure shows the snapback characteristic of an unsilicided device. As shown in FIGS. 3 and 4, the input potential Vin to the pad electrode 41 rises to a potential V1 and then becomes a breakdown mode in the area of the drain diffusion layer 52 directly below the gate electrode 51. After dropping to a potential Vsb, this input potential Vin rises again. The status of the transistor at this time is called a snapback state.
This snapback state occurs as parasitic bipolar transistors TrA and TrB shown in FIG. 3 are turned on. That is, impact ionization occurs directly under the drain diffusion layer 52 at the electrostatic destruction time and multiple holes are generated there, raising the potential of the semiconductor substrate 56. Thereafter, multiple electrons are diffused into the semiconductor substrate 56 from the source diffusion layer 53, so that the parasitic bipolar transistors TrA and TrB are turned on by this diffusion current. Since setting the buffer transistor into the snapback state can permit charges in the pad electrode 41 to be discharged efficiently, so that the performance of protecting the internal circuit can be enhanced.
Recently, a device whose diffusion layer has a silicided surface has been employed to increase the operational speed of a semiconductor device. The electrostatic destruction voltage of a device whose diffusion layer has a silicided surface becomes, for example, a voltage Vx1s as indicated by the solid line 71 while the electrostatic destruction voltage of a device whose diffusion layer has an unsilicided surface becomes, for example, a voltage Vx1 as indicated by the broken line 72.
When the N-channel MOS transistors 43 and 48 are formed in the layouts shown in FIGS. 2A and 2B, however, the guard ring layer 58 around the MOS transistors makes it difficult for the substrate potential at the peripheral portion of the buffer transistor to rise. Therefore, the parasitic bipolar transistor TrA formed at the peripheral portion of the buffer transistor becomes difficult to be turned on as compared with the parasitic bipolar transistor TrB formed at the center portion of the buffer transistor. This makes the peripheral portion of the buffer transistor more difficult to become the snapback state than the center portion of the buffer transistor. A variation in the way of going into the snapback state present in the substrate 56 cannot efficiently protect the internal circuit for the following reasons.
Suppose that the electrostatic destructon voltage Vx1 is greater than the potential V1 (Vx1&gt;V1) in a device whose diffusion layer has an unsilicided surface. When the pad voltage increases due to the application of a surge voltage, one of a plurality of MOS transistors connected in parallel becomes a snapback state first. Assume that this transistor is a transistor Tr1. This transistor Tr1 is most likely to trigger into snapback by a productional variation or the influence or the like of the guard ring layer 58. When the transistor Tr1 goes to the snapback state, the pad voltage is clamped to a potential Vsb. In a device of the 0.35 .mu.m rule, for example, the potential V1 is normally about 10 V, whereas the potential Vsb is about 6 V. It is apparent that the potential of the pad 41 drops significantly. When one transistor Tr1 gets into the snapback state, therefore, the other transistors cannot trigger into snapback.
After the transistor Tr1 triggers into snapback, the pad voltage rises again. Because the current flowing through the transistor Tr1 then has not reached the electrostatic destructon current Ix1, electrostatic destruction does not occur. When the pad voltage reaches the potential V1 thereafter, another transistor Tr2 goes into the snapback state. In this manner, the transistors sequentially trigger into snapback and all the transistors eventually go to the snapback state. Consequently, the whole transistors are discharged in the snapback state, thus ensuring a high protecting performance.
In the case of a silicided device, the above-described mechanism cannot be applied. Specifically, since the resistance of the diffusion layer of a silicided device is lower than that of an unsilicided device, the resistances of the areas equivalent to the emitter and collector of a bipolar transistor become lower. As indicated by the solid line 71 in FIG. 4, therefore, the inclination of the snapback characteristic after the transistor triggers into snapback becomes sharp. For example, the snapback resistance Rsnps of the silicided device is about 18 .OMEGA. while the snapback resistance Rsnp of the unsilicided device is about 30 .OMEGA., showing approximately 50% of difference between those resistances. When one transistor Tr1 in the parallel-connected transistors triggers into snapback, therefore, the current flowing through the transistor Tr1 reaches the electrostatic destruction current Ix1, destroying the transistor Tr1, before the next transistor Tr2 triggers into snapback. That is, with the silicided surface of the diffusion layer, even if rectangular gate electrodes are laid out in parallel and transistors are connected in parallel as shown in FIGS. 2A and 2B, after one transistor Tr1 is operated, this transistor Tr1 is broken before another transistor triggers into snapback.
This phenomenon occurs not only in a device having a diffusion layer with a silicided surface but also in a device having a diffusion layer with an unsilicided surface. That is, with the electrostatic destruction current of the transistors being Ix2 and the electrostatic destruction voltage being Vx2, when the electrostatic destruction voltage Vx2 is smaller than the potential V1 (Vx2&lt;V1), after one transistor Tr1 in the parallel-connected transistors triggers into snapback, the current flowing through the transistor Tr1 reaches the electrostatic destruction current Ix2, destroying the transistor Tr1, before another transistor triggers into snapback.
In view of the above, the conventional protection circuit cannot efficiently protect a circuit against an excess voltage.